Faculty profile
Anestis Dounavis
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Read how they describe their research on their Western University profile.
Latest funding
- $168,000
Design Automation Algorithms for High-Speed Integrated Circuits and Microsystems
NSERC · 2019 · Principal investigator
- $155,000
Electronic Design Automation Algorithms for Signal Integrity Analysis of High Speed Integrated Circuits
NSERC · 2014 · Principal investigator
- $100,000
Design automation algorithms of integrated circuits and microsystems
NSERC · 2009 · Principal investigator
No publications available.
Design Automation Algorithms for High-Speed Integrated Circuits and Microsystems
Principal investigators: Dounavis, Anestis
Keywords: signal integrity; high-speed interconnects; interconnect noise analysis; macromodeling; transmission lines; electromagnetic interference; numerical methods; circuit simulation; model-order reduction; sensitivity analysis
Electronic Design Automation Algorithms for Signal Integrity Analysis of High Speed Integrated Circuits
Principal investigators: Dounavis, Anestis
Design automation algorithms of integrated circuits and microsystems
Principal investigators: Dounavis, Anestis
Design/verification methodologies of VLSI circuits
Principal investigators: Dounavis, Anestis
From CIHR, NSERC and SSHRC funding decisions: CIHR since 2008, NSERC since 1991 and SSHRC since 1998, including their latest published competition results.
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Profile data last refreshed on September 26, 2026 from the university directory, publication records and CIHR, NSERC and SSHRC funding.